1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device which has a block write function to write the same data into a plurality of rows.
2. Description of the Related Art
In ordinary semiconductor memory devices, when data writing and reading are done for a memory cell of one address incorporated in a memory cell array which includes a plurality of memory cells arranged in a matrix, usually, one row of the memory cell array is selected by a row selection circuit and one column thereof is selected by a column selection circuit, whereby the memory cell disposed at the cross point is selected.
On the other hand, of the semiconductor memory devices for image processing, in order to obtain a high speed operation for the image processing, there has been a semiconductor memory device having a block write function in which the same data is written simultaneously to the memory cells of a plurality of continuous column addresses, for example, 4 addresses, and eight addresses and so on.
An example of such semiconductor device having the block write function is shown in FIG. 1.
The semiconductor memory device shown in FIG. 1 comprises a memory cell array 10 which includes a plurality of memory cells arranged in a matrix in row and column directions; a row selection circuit 20 which selects these memory cells arranged in the same row according to a row address signal ADR via word lines WL corresponding to each row of the memory cell; a column selection circuit 30 which selects a prescribed bit line among bit lines BL corresponding to each of the memory cell columns (hereinafter referred to as a column) according to a column address selection signal CS and transmits writing data DTw to the memory cell disposed at a cross point of the selected row and column and reads out (DTr) the data from this memory cell; and segment circuits SGC1x to SGCnx which divide the columns of the memory cell array 10 corresponding to each bit line BL into segments, each segment consisting of adjacent columns, for example, four columns. The semiconductor memory device further comprises a column address selection circuit 1x which includes segment circuits SGC1x to SGCnx and renders a prescribed column address signal among the column address selection signals CS to a selection level according to a segment address selection signal SAS, a subordinate bit of the column address signal (hereinafter referred to as a subordinate column address signal) ADCd, and a block write signal BW; and a plurality of selection segment address set circuits SSS1x to SSSnx, each of which corresponds to a corresponding one of the segment circuits SGC1x to SGCnx. The semiconductor memory device further comprises a segment address selection circuit 2x which includes selection segment address set circuits SSS1x to SSSnx and renders one among the segment address selection signals SAS to a selection level according to a superordinate bit of the column address signal (hereinafter referred to as a superordinate column address signal) ADCu.
A more detailed block diagram and circuit diagram of the column address selection circuit 1x and segment address selection circuit 2x are shown in FIGS. 2 and 3.
Each of the segment circuits SGC1x to SGCnx of the column address selection circuit 1x includes the selection column address set circuits (SCS1X to SCS4x/SCS5x to SCS8x/ . . . ) corresponding to the column included in the corresponding segment, each of the selection column address set circuit including AND type logic gates G11x and G13x and an OR type logic gate G12x as shown in FIG. 3. Furthermore, each of the selection segment address set circuits SSS1x to SSSnx of the segment address selection circuit 2x consists of an AND type logic gate.
Next, a column address selection operation of the semiconductor memory device will be described.
First, on normal writing and reading operation modes (hereinafter as a normal operation mode), the block write signal BW is in an inactive level at low level, and the selection column address set circuit SCS1x to SCSnx decodes the subordinate column address signal ADCd (including constituent bits A0 and A1, and inverted signals thereof A0* and A1*) to transmit the decoded signal to the logic gate G13x via the logic gate G12x.
On the other hand, the selection segment address set circuit SSS1x to SSSnx decodes the superordinate column address signal ADCu (including constituent bits A2 to A4 and inverted signals thereof A2* to A4*, and, in this case, "n" of SSSnx is 8), and renders one among the segment address selection signals SAS1 to SASn to a selection level ("1"). Then, the selection segment address set circuit SSS1x to SSSnx transmits it to the logic gate G13x of the selection column address set circuit of the corresponding segment circuit.
Accordingly, the column address selection signal (CS3) from the selection column address set circuit, for example, SCS3x, is rendered to a selection level. The column address set circuit includes the logic gate G12x to decode the subordinate column address signal ADCd in the segment circuit (SGC1x) corresponding to the segment address selection signal, for example, SAS1, at a selection level. The column corresponding to the column address selection signal (CS3) is selected by the column selection circuit 30. Specifically, one column among the columns of the memory cell array 10 is selected by the subordinate address signal ADCd and the superordinate address signal ADCu.
Subsequently, an operation in a block write mode will be described.
For example, as shown in the portion of the left of FIG. 4, it is assumed that the same data be written to the segments SG disposed from an address "a" to an address "b" in the memory region MA of the memory cell array 10. The column addresses and the segment addresses in the memory region MA are sequentially arranged such that the one disposed in the left end is the least significant address and the one disposed in the right end is the most significant address. In addition, in the segment SG in which addresses "a" and "b" of the column address are included, the column address (disposed on the subordinate side of the address "a" and disposed on the superordinate side of the address "b") to write data different from the foregoing data shall be included.
When rendering the block write signal BW to be an active level ("1"), all of the column address selection signals (CSi, i: column number) in the segment corresponding to the segment address signal selection signal (SASj, j: segment number) at the selection level will become the selection level. Accordingly, when the segment columns (a to c, d to b) are selected, in which the address "a" and "b" of the column address are included, with the block write signal BW kept at an inactive level, the segment column address selection operation is performed in the normal operation mode. In case of columns composed of segments SG interposed between the segments including the address "a" and "b" of the column address the segment address selection signal corresponding to the segments is sequentially rendered to the selection level, at the same time the block write signal is rendered to the active level and all of the column address selection signals included in this segment are rendered to the selection level. Therefore, selections of the columns included in each of the segments can be done simultaneously so that the writing operation will be performed quickly.
Furthermore, as shown in the portion of the right side of FIG. 4, it is usual that the memory region MA is divided into two areas composed of the subordinate side (0 to E/2) and the superordinate side (E/2 to E) and the same data is written to the address extents (a to b, and E/2+a to E/2+b) corresponding to these two areas. In this case, the column selection operation from the foregoing address "a" to the address "b" may be similarly performed also from the address "E/2+a" to "E/2+b".
In the foregoing conventional semiconductor device, when the same data is written to the segments ranging from the number "a" to the number "b" of the column address, and also when the column is included to which the different data from the foregoing data are written in the segment including the numbers "a" and "b" of the column address, writing and reading of data are performed one column by one column according to the similar operation to the normal writing operation, and for the segment interposed between the segments including the numbers "a" and "b" of the column address, the operations that all columns in this segment are selected and writing is sequentially performed for each segment are sequentially performed. Therefore, the selection and writing operations in the normal operation mode are needed, and, moreover, in the segments using the block write mode, the selection and writing operations are sequentially performed for every segment. Thus, the difficulty of the operation to write the same data to the prescribed extent quickly and the complexity of the operations are brought about. Even when the same data is written to a plurality of extents, the same selection and writing operations are sequentially performed for each extent, it is also difficult to perform a high speed operation.